Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing trend is given.